CVE-2020-10255

9.0 CRITICAL

📋 TL;DR

CVE-2020-10255 is a hardware vulnerability in DDR4 and LPDDR4 DRAM chips manufactured after 2015 that bypasses Target Row Refresh (TRR) mitigations against RowHammer attacks. Attackers can trigger bit flips in memory to escalate privileges, compromise cryptographic keys, and potentially achieve cross-VM access. This affects systems using vulnerable DRAM chips from SK Hynix, Micron, and Samsung.

💻 Affected Systems

Products:
  • Systems with DDR4/LPDDR4 DRAM chips from SK Hynix, Micron, Samsung manufactured after 2015
Versions: All versions using affected hardware
Operating Systems: All operating systems running on vulnerable hardware
Default Config Vulnerable: ⚠️ Yes
Notes: Single product models may use DRAM chips from different manufacturers, making supply chain tracking difficult. Cloud environments with shared hardware are particularly vulnerable.

📦 What is this software?

⚠️ Risk & Real-World Impact

🔴

Worst Case

Full system compromise including kernel privilege escalation, Sudo binary takeover, cross-tenant VM escape, and RSA key corruption leading to complete data breach.

🟠

Likely Case

Privilege escalation attacks against kernel or Sudo, potentially leading to unauthorized administrative access on affected systems.

🟢

If Mitigated

Limited impact if proper memory isolation and access controls are implemented, though hardware vulnerability remains.

🌐 Internet-Facing: MEDIUM
🏢 Internal Only: HIGH

🎯 Exploit Status

Public PoC: ⚠️ Yes
Weaponized: LIKELY
Unauthenticated Exploit: ✅ No
Complexity: HIGH

Exploitation requires physical or virtual memory access and specific access patterns to trigger bit flips. The TRRespass tool demonstrates proof-of-concept.

🛠️ Fix & Mitigation

✅ Official Fix

Patch Version: N/A

Vendor Advisory: N/A

Restart Required: No

Instructions:

This is a hardware vulnerability with no direct software patch. Contact hardware vendors for potential BIOS/firmware updates that may implement additional mitigations.

🔧 Temporary Workarounds

Enable ECC Memory

all

Use Error-Correcting Code (ECC) memory to detect and correct bit flips caused by RowHammer attacks.

Hardware configuration required - no command

Memory Isolation Controls

all

Implement strict memory isolation between processes and VMs to limit attack surface.

System-specific configuration required

🧯 If You Can't Patch

  • Segment critical systems from untrusted users/VMs
  • Implement strict access controls and monitoring for privilege escalation attempts

🔍 How to Verify

Check if Vulnerable:

Check DRAM manufacturer and model via dmidecode or similar hardware inventory tools. Run TRRespass tool from VUSec to test susceptibility.

Check Version:

dmidecode --type memory | grep -i manufacturer

Verify Fix Applied:

No complete fix exists. Verify ECC memory is enabled and functioning via system logs or hardware monitoring tools.

📡 Detection & Monitoring

Log Indicators:

  • Memory error corrections (ECC events)
  • Unexpected privilege escalation attempts
  • Kernel panic or system instability

Network Indicators:

  • N/A - local hardware attack

SIEM Query:

Search for: (EventID: 1 OR EventID: 41) AND (Memory OR ECC) OR (sudo OR privilege escalation anomalies)

🔗 References

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